1. Field of the Invention
The invention concerns a method and apparatus for synchronization of a clock signal generator.
2. Description of the Prior Art
In synchronous digital telecommunications exchange systems, the individual exchanges are synchronized from a central standard frequency installation which is at the highest hierarchy level of the system. The central clock generators of the individual digital exchanges are therefore synchronized to a signal reference frequency which is transmitted by a network center of a higher order or the same order, and provisions are made to keep the reference frequency ready for use in the system by way of an alternative route to which it is possible to automatically switch to in the event of trouble.
The reference frequencies are transmitted by way of existing digital signal connections to the respective exchanges, where they are extracted from the incoming digital signal currents. The reference frequencies are thus subject to high-frequency and low-frequency phase fluctuations (jitter and drift).
Phase control circuits of the central clock generators in the individual exchanges, which are responsible for synchronization to a reference frequency, are designed in such a way that they eliminate the high-frequency periodic phase fluctuations (jitter). They take into account the low-frequency phase fluctuations (drift) in frequency regulation of the clock generator, so they act as a low pass filter with regard to the phase fluctuations. Elimination of the high-frequency periodic phase fluctuations is then accomplished by averaging over certain periods of time.
With longer-lasting interruptions in the reference frequency arriving at an exchange, the frequency is switched to a different reference frequency which is supplied from another exchange on an alternative route as mentioned above. If the interruptions in the reference frequency are of only brief duration, e.g., shorter than 2 minutes, however, no such switch is made and the original reference frequency is used again for synchronization after it returns. In the time during which the reference frequency is out, the clock generator is free running, although this does not lead to any significant synchronization errors because of the relatively high stability of the clock generator and the brief interruption time assumed here. However, because of the above-mentioned periodic phase fluctuations, there may be some phase displacement when restarting, and this effect can be cumulative when such restarting is repeated. In combination with jitter, this is the case when recurrence of the reference clock signal takes place at the time of a maximum in this high-frequency phase fluctuation, so there is a sudden phase shift in comparison with the average phase prevailing before the outage. In order for the drift in the reference clock frequency not to lead to a synchronization error due to the interruption and resumption, care must be taken to assure that the long-term phase relationship existing between the signal at the output and the input of the controller at the moment of the interruption is preserved.
A known circuit arrangement, which takes into account both aspects so it assures that the aforementioned phase relationship is maintained while also preventing the control system from locking on an extreme jitter value, is shown in FIG. 1. Upstream from the actual controller (PLL2) of this arrangement, which synchronizes the clock frequency f.sub.n to the reference frequency f.sub.R, there is a second controller (PLL1) whose function is to filter out the high-frequency jitter of the reference frequency f.sub.R. This arrangement also has a number of frequency dividers, as a result of which, at an output frequency f.sub.n of 4096 kHz a phase comparison is performed at 4kHz by the second controller (PLL1) and a phase comparison at 64 kHz is performed by the actual controller (PLL2). If the reference frequency f.sub.R is lost, controller (PLL2) is short circuited with the help of switch S, so the phase position at the controller output does not change during the outage time.
With the help of this arrangement, occurrence of an error in synchronization which is possible due to the drift in the reference frequency is largely avoided, but there is a locking error here of 1/4096 kHz=244 ns because of the jitter in returning to the normal state. Because of the difference in free running properties of the two phase control circuits (PLL1) and (PLL2) this locking error tends in one direction so it is cumulative when the switching operations are repeated several times. The purpose of the present invention is to greatly improve the process for synchronization of a clock generator of the type defined initially so that such errors can largely be avoided in the case of loss and resumption of the reference frequency.